1. Field of the Invention
The present invention relates to a repair fuse circuit and, more particularly, to a repair fuse circuit improving a latch operation using flash memory cells, by initializing a cross-coupled latch circuit in a predetermined high voltage level.
2. Description of the Related Arts
In general, a repair fuse circuit using flash memory cells has used a cross-coupled latch circuit in which the latch operation is naturally carried out by applied power voltage.
Referring now to FIG. 1A, the conventional repair fuse circuit includes two p-channel MOS transistors MP1 and MP2, two flash memory cells FC1 and FC2, n-channel MOS transistor MN1 and an inverter INT1. It should be noted that the flash memory cell FC2 consists of two flash memory cells connected in parallel.
The source of each of the p-channel MOS transistors MP1 and MP2 is commonly coupled to a power supply Vcc and the drain of p-channel MOS transistor MP1 is coupled to the drain of the flash memory cell FC1. Further, the drain of p-channel MOS transistor MP2 is coupled to the drain of the flash memory cell FC2. Accordingly, voltage from the power supply Vcc is applied to each drain of the two flash memory cells FC1 and FC2 via the p-channel MOS transistors MP1 and MP2.
In case where the flash memory cells are erased by the ultraviolet rays and the repair operation is not carried out, the amount of current flowing away through the flash memory cell FC2 may be twice as much as that through the flash memory cell FC1 because the flash memory cell FC2 consists of two memories which are connected in parallel and the flash memory FC1 consists of only one memory cell.
Accordingly, the drain of the flash memory cell FC2 is in a ground voltage level because the current flowing through the flash memory cell FC2 is passed through the n-channel MOS transistor MN1 and the drain of the flash memory cell FC1 is in a voltage level of Vcc. At this time, as shown in FIG. 1B, the gate of the n-channel transistor MN1 receives a fuse read signal FUSEREAD, As shown in FIG. 1B, at a node N2, the drain of the p-channel MOS transistor MP2, the drain of the flash memory cell FC2, the gates of the p-channel MOS transistor MP1 and the flash memory cell FC1 are connected is in a high voltage level and, at a node N1, the drain of the p-channel MOS transistor MP1, the drain of the flash memory cell FC1, the gates of the p-channel MOS transistor MP2 and the flash memory cell FC2 are connected is in a low voltage level. As a result, the output from the inverter INT1 is a fuse output signal of 0 V.
In case where the repair is carried out by programming the flash memory cell FC2, since no current flows through the flash memory cell FC2, the drain of the flash memory cell FC2 is in a high voltage level of Vcc and the drain of the flash memory cell FC1 is in a low voltage level of 0 V.
When a latch operation for the initialization may be erroneously performed in a low voltage level, the repair may be not performed. However, in this case, it appears as if the repair has been performed. That is, typically, the repair circuit is initialized in a low voltage level, but the latch operation may be erroneously performed. Although the power supply Vcc is going from low to high, this latch operation may be not corrected because the repair fuse circuit uses a cross-coupled structure.